Logic voltage level translation is required in many electronic systems. One integrated circuit may be operating at a lower power supply voltage level (e.g. 1.2V, 1.5V or 3.3V, etc.) while a second integrated circuit may be operating at much higher voltage level (e.g. 5.0V). When the integrated circuits communicate with each other, the voltage levels of the driving integrated circuit must be compatible with the threshold voltages of the receiving integrated circuit. These threshold values differ based on the amplitude of the power supply voltage sources of the two integrated circuits. When the integrated circuits communicate with each other and have differing power supply voltage levels, a level-translation solution is needed. The output driver level for a high or logic 1 output must be greater than the threshold level of the receiver input level for the input to receive the high input level or logic 1. The output driver level for a low or logic 0 output must be less than the threshold level of the receiver input level for the input to receive the low input level or logic 0. Further, the output driver levels must meet the tolerance variations of the receiver even when the driver is at its extremes of tolerance.
FIGS. 1 and 2 illustrate a driver and receiver of an inter-chip connection between first integrated circuit chip 5 and a second integrated circuit chip 15 of the prior art. A microcontroller is placed on the first integrated circuit chip 5 and is powered by a low power supply voltage source VDD_JO (e.g. 1.5V). An output signal of the microcontroller of the first integrated circuit chip 5 is applied to a driver circuit 10. The output of the driver circuit 10 is connected to wiring. The wiring is then connected to an input of the second integrated circuit chip 15 that has a high power supply voltage source VDD (e.g. 5V). An input buffer 20 acts as a receiver for the integrated circuit chip 15. The input buffer, as shown in FIG. 2, consists of a CMOS inverter circuit 22. The CMOS inverter circuit 22 has an NMOS transistor MN1 and a PMOS transistor MP1. The gates of the NMOS transistor MN1 and a PMOS transistor MP1 are connected together and to the input of the connection from the wiring between the first integrated circuit chip 5 and a second integrated circuit chip 15. The source of the PMOS transistor MP1 is connected to the power supply voltage source VDD and the source of the NMOS transistor MN1 is connected to the substrate of the integrated circuit chip 15 that is usually the ground reference source. The drains of the NMOS transistor MN1 and a PMOS transistor MP1 are connected together and to the input of the of the inverter circuit 24. In most instances the inverter circuit 24 is equivalent to the CMOS inverter circuit 22.
When the driver 10 is set to a logical 0 or a low output state, the NMOS transistor MN1 is turned off and the PMOS transistor MP1 is turned on and the output of the inverter circuit 22 is at a logical 1 or a high output state. When the driver 10 begins to change from the low output state to the high output state, the output voltage begins to rise. The NMOS transistor MN1 begins to turn on and the PMOS transistor MP1 begins to turn off. As the amplitude of the output of the driver 10 rises to its maximum amplitude and the NMOS transistor MN1 is turned on to saturation. However, the maximum voltage of the high level of the driver 10 may not be sufficient to turn off the PMOS transistor MP1 and a shoot through current is transferred through the PMOS transistor MP1 and the NMOS transistor MN1. The shoot through current maybe excessive and cause damage or are a waste of power.
FIGS. 3 and 4 are schematics illustrating an example of a solution to the shoot through problem described in FIGS. 1 and 2 of the prior art. Referring to FIG. 3, The receiver 25 includes an input buffer 30 that receives the input voltage VIN at its input. The input buffer 30 is connected to a low power supply voltage source VDD_IO that has the same amplitude as that connected to the first integrated circuit chip 5 of FIG. 1. The receiver is also connected to the ground reference source. The input buffer is configured to have output voltage levels that range from approximately the ground reference level and approximately the voltage level of the low power supply voltage source VDD_IO. The output of the input buffer is connected to an input of a level shifter 35. The level shifter 35 is connected to the low power supply voltage source VDD_IO and the high power supply voltage source VDD. A level shifter circuit is known in the art to be configured for shifting an amplitude swing of a signal to an amplitude swing of a larger range. Adding the low power supply voltage source VDD_IO externally to the second integrated circuit chip increases die cost, pin count and PCB traces.
In FIG. 4, the input buffer 30 has an NMOS transistor MN2 and a PMOS transistor MP2. The gates of the NMOS transistor MN2 and a PMOS transistor MP2 are connected together and to the input of the connection from the wiring between the first integrated circuit chip 5 and a second integrated circuit chip 15. The source of the PMOS transistor MP2 is connected to the low drop out power supply 40 to receive the low power supply voltage VDD_IO and the source of the NMOS transistor MN2 is connected to the ground reference source. The drains of the NMOS transistor MN2 and a PMOS transistor MP2 are connected together and to the input of the of the level shifter 35. The level shifter 35 shifts the amplitude of the output of the buffer from the swing from the ground reference level to that of the low power supply voltage source VDD_IO to a voltage swing from the ground reference level to that of the low power supply voltage source VDD.
The low drop out power supply 40 generates the low power supply voltage VDD_IO for application to the input buffer and the level shifter 35. The low drop out power supply 40 the low power supply voltage VDD_IO is generated internally to save pin count. This low drop out power supply 40 has to manage transient current of input buffer 30 and level shifter 35. The design of low drop out power supply 40 is more difficult if a large capacitor on low power supply voltage source VDD_IO is not allowed. And the additional power for low drop out power supply 40 could be large.
FIG. 5 is a schematic diagram of an input receiver capable of alleviating shoot through of the prior art. The input receiver has a number of PMOS transistors MP3, MP4, and MP5 connected in series. The source of the first PMOS transistor MP3 is connected to the power supply voltage source VDD. The drain of the last PMOS transistor MP5 is connected to the drain of the NMOS transistor MN3. The source of the NMOS transistor MN3 is connected to the ground reference source. The gates of the PMOS transistors MP3, MP4, MP5, and the NMOS transistor MN3 are connected together and to the input of the integrated circuit to receive the input voltage VIN. The connection between the drains of the PMOS transistor MP5, and the NMOS transistor MN3 is connected to the input of the inverter 50. While the shoot through is not eliminated, it may be lowered to an acceptable level.